This invention relates to connection error checking which occurs during circuitry design.
Integrated circuits typically include various combinational elements (e.g., AND gates, OR gates, NAND gates, XOR gates, etc.) and state elements (e.g., latches, flip-flops, etc.) in their design. Each of these combinational and state elements are discrete elements that the engineer places into the circuit design.
As integrated circuit designs get increasingly complex, engineers need enhanced tools to aid them in the design process. The design process for a semiconductor chip can typically be broken down into subtasks (i.e., design, capture, documentation, compilation, and debug). One typical way to design a complex semiconductor chip would be to have an architecture team and an implementation team. An architecture team provides various models (i.e., a specification and a object-based (e.g., C++) model) of the design to the implementation team. The implementation team tests and simulates the circuit using various tools (e.g., Synopsis VCS Verilog Simulator, etc.). Any resulting bugs/errors can be collected in a list that is used by the architecture team to modify the circuit design. The modified design can then be given back to the implementation team for further testing.